A semiconductor integrated circuit (IC) has a large number of electronic components, such as transistors, logic gates, diodes, wires, etc., that are fabricated by forming layers of different materials and of different geometric shapes on various regions of a silicon wafer. The design of an integrated circuit transforms a circuit description into a geometric description called a layout. The process of converting specifications of an integrated circuit into a layout is called the physical design.
Chip designers often use electronic design automation (EDA) software tools to assist in the design process. Chip design using EDA software tools generally involves an iterative process whereby the chip design is gradually perfected. A top-down design methodology is commonly employed using hardware description languages (HDLs), such as Verilog or VHDL for example, by which the designer creates an integrated circuit by hierarchically defining functional components of the circuit, and then decomposing each component into smaller and smaller components.
The various components of an integrated circuit are initially defined by their functional operations and relevant inputs and outputs. From the HDL or other high level description, the actual logic cell implementation is typically determined by logic synthesis, which converts the functional description of the circuit into a specific circuit implementation. The logic cells are then “placed” (e.g., given specific coordinate locations in the circuit layout) and “routed” (e.g., wired or connected together according to the designer's circuit definitions). The placement and routing software routines generally accept as their input a flattened netlist that has been generated by the logic synthesis process. This flattened netlist identifies the specific logic cell instances from a target standard cell library, and describes the specific cell-to-cell connectivity. In the area of custom designs, where complexity is less than digital design, the ‘logic synthesis’ approach is not taken, and the user can instead directly conduct placement and routing based on the logic connection blueprint (schematic). In addition, with respect to custom designs, users may hand-craft their own proprietary library of components, rather than using standard-cell library, just for better optimization. In both design styles, automatic or assisted placement and routing are commonly used to facilitate the process and gain advantage on fast turn-around time from design to manufacturing, and then to final products.
Conventionally, routing is accomplished using a two-staged process of first performing global routing followed by detail routing. A global router does not normally make any specific connections, but provides a general plan for making the connections. The router first global routes the whole chip or large portions of the chip before implementing detail routing of any part or whole of the chip. During detail routing, the detailed router determines the exact location and layers for each interconnect, based upon the set of metal rules that have been provided to the chip designer. However, conventional routers that use the global route/detail route approach are implemented with a distinctive separation between the global router and the detail router which prevents effective and efficient interaction between the two types of routers.
Conventional “area-based” routers include techniques that implement the ability to look at each area of the design, and to thoroughly handle any routing activities that are needed to route any nets through that area of the design currently being focused on. However, since this approach analyzes and routes each small portion of the design independently from one another, this means that there is very little structural control over the overall topology that can be applied during the routing process.
Structural routing approaches have also been attempted, where a user provides an upfront structure to the topology in a structural global routing stage, followed by the automated detail routing implementation. However, conventional structural routers also suffer from many deficiencies. One significant problem with known structural routers is that during the detail routing stage (such as during “rip up and re-route” processing), topology controls are lost and thus the final routed design may be significantly different from the originally intended topological structure. Another problem with this approach is that it requires manual processing by the user to define the upfront structure, which is especially problematic given that modern electronic designs have become extremely complicated with immense numbers of components, objects, and rules that need to be considered even to begin a manual process to insert any element into the design.
Therefore, there is a need for an improved approach to implement routing that that can adequately address these and other problems with the conventional tools.